Test MP+dmb.sy+[fr-rf]-addr-wsi-rfi-ctrl

AArch64 MP+dmb.sy+[fr-rf]-addr-wsi-rfi-ctrl
"DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Wsi Rfi DpCtrldR Fre"
Cycle=Rfi DpCtrldR Fre DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Wsi
Relax=
Safe=Rfi Rfe Fre Wsi DMB.SYdWW DpAddrdW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Wsi Rfi DpCtrldR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X9=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | MOV W4,#1           |             ;
 STR W2,[X3] | STR W4,[X5,W3,SXTW] |             ;
             | MOV W6,#2           |             ;
             | STR W6,[X5]         |             ;
             | LDR W7,[X5]         |             ;
             | CBNZ W7,LC00        |             ;
             | LC00:               |             ;
             | LDR W8,[X9]         |             ;
Observed
    z=2; y=2; x=1; 1:X8=1; 1:X7=2; 1:X2=0; 1:X0=2;
and z=2; y=1; x=1; 1:X8=1; 1:X7=2; 1:X2=0; 1:X0=2;
and z=2; y=1; x=1; 1:X8=0; 1:X7=2; 1:X2=0; 1:X0=2;
and z=2; y=2; x=1; 1:X8=1; 1:X7=2; 1:X2=0; 1:X0=1;
and z=2; y=1; x=1; 1:X8=1; 1:X7=2; 1:X2=0; 1:X0=1;
and z=2; y=1; x=1; 1:X8=0; 1:X7=2; 1:X2=0; 1:X0=1;